Intel 8080 Instruction Set Reference¶

This document provides a complete reference for the Intel 8080 microprocessor instruction set.

Register Conventions ¶

The following conventions are used throughout this document:

8-bit registers are encoded as 3-bit fields:

16-bit register pairs are encoded as 2-bit fields:

Register Pair Encoding¶
Code	Pair	Description
`00`	BC	B:C as 16-bit register
`01`	DE	D:E as 16-bit register
`10`	HL	H:L as 16-bit register
`11`	SP	Stack pointer (PSW for PUSH/POP)

Condition codes for conditional instructions:

Condition Codes¶
Code	Mnemonic	Condition
`000`	NZ	Zero flag not set
`001`	Z	Zero flag set
`010`	NC	Carry flag not set
`011`	C	Carry flag set
`100`	PO	Parity odd (parity flag not set)
`101`	PE	Parity even (parity flag set)
`110`	P	Positive (sign flag not set)
`111`	M	Minus (sign flag set)

The following flags may be affected by instructions:

For instructions that take operands:

The flag columns show which flags are affected:

Data Transfer Instructions¶
Instruction	Encoding	Description
`MOV D,S`	`01DDDSSS`	Move register to register
`MVI D,#`	`00DDD110 db`	Move immediate to register
`LXI RP,#`	`00RP0001 lb hb`	Load register pair immediate
`LDA a`	`00111010 lb hb`	Load A from memory
`STA a`	`00110010 lb hb`	Store A to memory
`LHLD a`	`00101010 lb hb`	Load HL from memory
`SHLD a`	`00100010 lb hb`	Store HL to memory
`LDAX RP`	`00RP1010`	Load indirect through BC or DE only
`STAX RP`	`00RP0010`	Store indirect through BC or DE only
`XCHG`	`11101011`	Exchange DE and HL content

Arithmetic Instructions¶
Instruction	Encoding	Flags	Description
`ADD S`	`10000SSS`	ZSPCA	Add register to A
`ADI #`	`11000110 db`	ZSPCA	Add immediate to A
`ADC S`	`10001SSS`	ZSPCA	Add register to A with carry
`ACI #`	`11001110 db`	ZSPCA	Add immediate to A with carry
`SUB S`	`10010SSS`	ZSPCA	Subtract register from A
`SUI #`	`11010110 db`	ZSPCA	Subtract immediate from A
`SBB S`	`10011SSS`	ZSPCA	Subtract register from A with borrow
`SBI #`	`11011110 db`	ZSPCA	Subtract immediate from A with borrow
`INR D`	`00DDD100`	ZSPA	Increment register
`DCR D`	`00DDD101`	ZSPA	Decrement register
`INX RP`	`00RP0011`		Increment register pair
`DCX RP`	`00RP1011`		Decrement register pair
`DAD RP`	`00RP1001`	C	Add register pair to HL (16-bit)
`DAA`	`00100111`	ZSPCA	Decimal Adjust accumulator

Logical Instructions¶
Instruction	Encoding	Flags	Description
`ANA S`	`10100SSS`	ZSPCA	AND register with A
`ANI #`	`11100110 db`	ZSPCA	AND immediate with A
`ORA S`	`10110SSS`	ZSPCA	OR register with A
`ORI #`	`11110110 db`	ZSPCA	OR immediate with A
`XRA S`	`10101SSS`	ZSPCA	Exclusive OR register with A
`XRI #`	`11101110 db`	ZSPCA	Exclusive OR immediate with A
`CMP S`	`10111SSS`	ZSPCA	Compare register with A
`CPI #`	`11111110 db`	ZSPCA	Compare immediate with A

Rotate Instructions¶
Instruction	Encoding	Flags	Description
`RLC`	`00000111`	C	Rotate A left
`RRC`	`00001111`	C	Rotate A right
`RAL`	`00010111`	C	Rotate A left through carry
`RAR`	`00011111`	C	Rotate A right through carry

Complement and Carry Instructions¶
Instruction	Encoding	Flags	Description
`CMA`	`00101111`		Complement A
`CMC`	`00111111`	C	Complement Carry flag
`STC`	`00110111`	C	Set Carry flag

Branch Instructions¶
Instruction	Encoding	Description
`JMP a`	`11000011 lb hb`	Unconditional jump
`Jccc a`	`11CCC010 lb hb`	Conditional jump
`CALL a`	`11001101 lb hb`	Unconditional subroutine call
`Cccc a`	`11CCC100 lb hb`	Conditional subroutine call
`RET`	`11001001`	Unconditional return from subroutine
`Rccc`	`11CCC000`	Conditional return from subroutine
`RST n`	`11NNN111`	Restart (Call n*8)
`PCHL`	`11101001`	Jump to address in HL

Stack Instructions¶
Instruction	Encoding	Description
`PUSH RP`	`11RP0101`	Push register pair on stack (RP=11 pushes PSW)
`POP RP`	`11RP0001`	Pop register pair from stack (RP=11 pops PSW, affects all registers)
`XTHL`	`11100011`	Swap HL with top word on stack
`SPHL`	`11111001`	Set SP to content of HL

I/O Instructions¶
Instruction	Encoding	Description
`IN p`	`11011011 pa`	Read input port into A
`OUT p`	`11010011 pa`	Write A to output port